1. Technical Field
A NAND flash memory device is disclosed in which loading times of a drain select line (hereinafter, referred to as ‘DSL’) and a source select line (hereinafter, referred to as ‘SSL’) are reduced through a reduction in resistance of a DSL and a SSL of the disclosed NAND flash memory device.
2. Description of the Related Art
The operation of a memory cell of a NAND flash memory device is performed on a block basis. The operation of such a memory cell is performed with a selected block separated from a non-selected block. The DSL and SSL of a block that is selected when a memory cell operates are inputted with a bias, as shown in Table 1 below. On the contrary, the DSL and SSL of a non-selected block are grounded. In this time, as shown in FIG. 13, the DSL/SSL are located at the top and the bottom of a string, respectively, so that a string is selected. Also, the string consists of 16 or 32 memory cells that are serially connected.
TABLE 1Selected BlockNon-selected BlockDSLVCC (Power Supply Voltage)GND (Ground Voltage)SSLVCC (Power Supply Voltage)GND (Ground Voltage)
As a NAND flash memory device operates in a serial manner, the memory cells operate sequentially on a block basis. Therefore, the DSL/SSL change from the power supply voltage to the ground voltage or from the ground voltage to the power supply voltage. The DSL/SSL structure of a NAND flash memory device, which is currently being used, is located adjacent to a X-decoder 20. Thus, there is a difference in RC delay depending upon the location of the DSL/SSL. In other words, a cell that is located at the farthest from the X-decoder 20 undergoes the worst effect compared to a cell that is located adjacent to the X-decoder 20. This is because only a first poly resistor is used and the cell is located at the farthest from a bias input unit.